Integrated circuits implemented in SOI technology offer a certain number of advantages. Such circuits generally have lower power consumption for equivalent performance. Such circuits also cause lower parasitic capacitances, thereby improving switching speed. Furthermore, the latchup phenomenon encountered by CMOS transistors in bulk technology can be avoided. Such circuits are therefore particularly suitable for SOC or MEMS applications. It is also noted that SOI integrated circuits are less sensitive to the effects of ionizing radiation and are thus more reliable in applications where such radiation can cause operating problems, notably in space applications. SOI integrated circuits can notably include SRAM memories or logic gates.
The reduction of the static consumption of logic gates while increasing their switching speed is the subject of many studies. Some integrated circuits currently under development simultaneously integrate low-consumption logic gates and logic gates with a high switching speed. In order to generate these two types of logic gates on the same integrated circuit, the threshold voltage of some transistors of the fast-access logic gates is lowered, and the threshold voltage of other transistors of the low-consumption logic gates is increased. In bulk technology, the modulation of the threshold voltage level of transistors of the same type is carried out by differentiating the doping level of their channel. However, in FDSOI (Fully Depleted Silicon On Insulator) technology, the doping of the channel is more or less zero (1015 cm−3). Thus, the doping level of the channel of the transistors cannot therefore reveal substantial variations, which prevents the threshold voltages from being differentiated in this way. One solution proposed in some studies for implementing transistors of the same type with different threshold voltages is to integrate different gate materials for these transistors. However, the practical implementation of an integrated circuit of this type proves technically challenging and economically prohibitive.
In order to have different threshold voltages for different transistors in FDSOI technology, it is also known to use a biased ground plane arranged between a thin insulating oxide layer and the silicon substrate (known as UTBOX technology). By adjusting the doping and biasing of the ground planes, a range of threshold voltages can be defined for the different transistors. This will therefore provide low threshold voltage transistors, known as LVT (typically 400 mV), high threshold voltage transistors, known as HVT (typically 550 mV), and medium threshold voltage transistors, known as SVT (typically 450 mV).
Some publications have proposed developments of the structures of FDSOI integrated circuits. A practical problem that arises with any technological development relating to circuits of this type is that existing design tools may prove to be incompatible or may require substantial computing developments.
Thus, in the industry, the designers of electronic circuits for the manufacturers of semiconductors use computer-assisted design (CAD). Large circuits are in fact too complex to be designed manually and require appropriate computing tools, notably to avoid the risks of design errors. In fact, for current technological nodes, many parameters must be taken into account to avoid malfunction or destruction of the circuits. CAD uses a functional input specification. This functional specification describes the desired function of the circuit, as well as non-functional constraints (surface area, cost, power consumption, etc.). CAD provides a representation in the form of an output computer file (generally in GDSII or, more recently, OASIS format). This computer file defines the drawings of the masks of the integrated circuit to be implemented, in such a way that these masks can be manufactured. The masks that are produced are then used for the production of the circuit in the semiconductor production units during photolithography steps. CAD is divided up into a plurality of steps.
Starting with the functional specification of the circuit, the design and overall architecture of the integrated circuit are defined during a first step. The complete system (hardware and software) is thus modeled at a very high level in order to validate the performance of the chosen architecture in relation to the requirements of the application. The architecture of the integrated circuit is generally designed in Verilog, VHDL, SPICE or other languages.
An optimization step is then carried out (known as floorplanning) This step entails the creation of a map of the placements of the logic gates on the chip, the sources and bondings, the inputs/outputs, and the macro circuits (complex components such as the processors, DSP, memories, etc.).
A logical synthesis of the circuit is then carried out. In this step, the circuit is modeled at Register Transfer Level (RTL). This modeling describes the implementation of the integrated circuit in the form of sequential elements and logical combinations between the different inputs/outputs of the sequential elements and primary inputs/outputs of the integrated circuit. The modeling provides a network made up of logic gates and rudimentary elements. This modeling is generally coded with a dedicated language such as Verilog or VHDL. RTL modeling is automatically synthesizable into combinatorial (AND, OR, multiplexer gates, etc.) and sequential (synchronous D flip-flops, etc.) logic gates originating from a standard cell library. The placement of the elements is not yet specified at this stage and occurs in the form of a list of elements necessary for performing the desired functions.
A circuit behavioral synthesis, also known as a high-level synthesis or algorithmic synthesis, is then carried out. The time behavior of the generated RTL model is then simulated. Each interconnection signal is determined according to described input stimuli (generally in the same language as the RTL model). If the circuit to be simulated contains a processor, a corresponding executable program is defined in the form of binary memory content. The memory containing the program code and data (FLASH or SRAM, for example) can also be modeled with the same language, but at a higher level of abstraction than the RTL.
The algorithmic synthesis is not necessarily enough to guarantee the absence of design errors for the following reasons, since:                the generation of the stimuli is carried out by the designer and does not allow exhaustive functional tests to be carried out for reasons of time;        the logical simulators are relatively slow. For a complex circuit, several days of simulation may be necessary, which limits the number of simulations that can be carried out.        
During a logical synthesis step, the RTL model of the circuit is transformed into a description at the logic gates level (generation of the gate netlist). A library of available logic ports is provided for this purpose. This library generally provides a collection of several hundred logic elements (such as AND, OR, flip-flop gates, etc.). This library depends on the etching fineness of the circuit (for example 32 nm or 22 nm) and the cell drawing rules according to the production process of the manufacturer.
The user must also provide logical synthesis constraints, such that the operating frequency of the circuit, its conditions (supply voltage range, temperature range, spread of the gate transit times linked to the production process), the departure and arrival time constraints on the primary and secondary inputs of the circuit, the load model linked to the interconnection wires that will connect the gates or the maximum size of the circuit on the silicon substrate.
The synthesis tools generally work on synchronous digital integrated circuits of which the sequential elements are timed by a single clock. There may possibly be a plurality of clock domains, combining a set of sequential and combinatorial elements. The logical synthesis tool of a synchronous circuit generally proceeds in a plurality of steps:                transformation of the RTL model into generic combinatorial and sequential logical elements (independently from the target library) according to mathematical algorithms;        replacement of the generic logical elements with those originating from the target library. For this purpose, it chooses logical elements observing the constraints of time and space given by the user. Transit time analysis calculations are then carried out on all of the logical paths of the circuit in order to make sure that they observe the time constraints (operating frequency of the circuit). If the results are not conclusive, the tool attempts to use other ports available in the library to achieve the required result. It is thus customary in a library to have many ports performing the same logical function but with different sizes and fan-outs;        when the time constraints are observed, the synthesis tool has some time margins on some paths. It can then optimize the design of the circuit by replacing some gates with others that have lower requirements in terms of power consumption and silicon size, while continuing to observe the time constraints.        
The logical synthesis provides a computer file representing the instantiation of the gates of the target library and their interconnection and representing the integrated circuit (gate netlist). Different formats of this type of representation exist, notably the Verilog format, the VHDL format or the EDIF format.
The logical synthesis is followed by a place and route step. During this step, the different components of the integrated circuit defined in the gate netlist are automatically placed and connected according to the problem to be solved. The place and route process is a difficult optimization problem that requires metaheuristic techniques. The place and route step is then followed by the generation of the topography of the etching masks. During the logical synthesis of a circuit in UTBOX-FDSOI technology, in order to have as little impact as possible on the design process and the CAD tools already available, it is known to carry out a step of placing and routing of standard cells selected from a library including Bulk technology components. Automated transformations are then carried out following this place and route step, to convert the circuit defined in Bulk technology into a circuit in UTBOX-FDSOI technology. An automated transformation of this type can notably be carried out following the place and route step, in order to proceed with the generation of the topography of the etching masks, wherein a large number of parameters of the standard cells may be identical in Bulk technology or in UTBOX-FDSOI technology.
The logical synthesis of the circuit in UTBOX-FDSOI technology may also be carried out with a step of placing and routing of standard cells selected from a library directly including UTBOX-FDSOI components.
The standard cells of such a library include for the most part a pair of an nMOS transistor and a pMOS transistor implemented in an upper layer of silicon. This silicon layer overhangs an insulating oxide layer, of so-called ultrafine thickness, typically less than 50 nm. A ground plane or rear gate is disposed under the oxide layer of the nMOS and a ground plane or back gate is disposed under the oxide layer of the pMOS. Each ground plane is biased via a respective well passing under a deep isolation trench. The threshold voltage of the transistors is adjusted notably by applying appropriate biasing voltages to the wells. In order to increase the possibilities for adjusting the threshold voltages, the doping of the ground plane can be of the N-type or P-type, for either the nMOS transistor or the pMOS transistor. The ground planes of the pMOS transistors are biased by an N-type doping well. The ground planes of the nMOS transistors are biased by a P-type doping well. Such an association of the wells and transistors will be referred to below as PPNN.
Moreover, while the well of the pMOSs is normally biased to a voltage Vdd and the well of the nMOSs is normally biased to a voltage Gnd, these voltages may be modulated to adapt the threshold voltages of the transistors. An FBB (Forward Back Biasing) may notably be applied. Such a biasing consists in applying Gnd+ΔV to the well of the nMOSs and Vdd-ΔV to the well of the pMOSs. In use, the applied voltage variation ΔV is limited. In fact, ΔV is kept below a value Vdd/2 in order to avoid a diode junction leading directly between the P-type well and the N-type well.
To enable a greater value of ΔV (and thus lower the threshold voltage in order to increase the switching speed of some transistors), it has been proposed to bias the ground planes of the pMOSs by means of P-type doping wells, and to bias the ground planes of the nMOSs by means of N-type doping wells. Such an association of the wells and transistors will be referred to below as PNNP. However, while the PPNN association enables the relatively simple generation of the topography of the circuit through the automation of modifications of a topography originating from the placing and routing of standard Bulk cells, the same does not apply to a PNNP association.
If a placing and routing of standard Bulk cells or PPNN is then simply carried out, and the dopings of the wells of all standard cells envisaged during the generation of the topography of the masks are automatically inverted, a certain number of non-functional standard cells will then occur. The repetition cells (referred to as “well tap” cells) and the diodes protecting against the antenna effects (diodes of this type are notably referred to by the term “diode antenna”, in order to protect against the charge accumulation phenomenon during the manufacturing process referred to as the “antenna effect”) cannot thus operate correctly with a simple inversion of the doping of their well. With the biases applied to their well, the well tap cells would form directly biased diodes. The protection diodes would no longer form a diode and would be non-functional.
To generate the topography of the masks, the designer must then replace these standard cells with specific standard cells, then restart a place and route step to adapt the interconnections of these standard cells with higher-level metal lines or move some standard cells.
However, a new place and route step is long and laborious and prolongs the duration of the circuit design process. Consequently, the generation of a topography of PNNP masks is clearly more laborious than the generation of a topography of PPNN masks.